Boxis R700 User Manual Page 51
- Page / 392
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
ATI R700 Technology
Conditional Execution 3-15
Copyright © 2009 Advanced Micro Devices, Inc. All rights reserved.
3.6.5 Stack Allocation
Each program type has a stack for maintaining branch and other program states.
The maximum number of available stack entries is controlled by a host-written
register or by the hardware implementation of the processor. The minimum
number of stack entries required to correctly execute a program is determined by
the deepest control-flow instruction.
Each stack entry contains a number of subentries. The number of subentries per
stack entry varies, based the number of thread groups (simultaneously executing
threads on a SIMD pipeline) per program type that are supported by the target
processor. If a processor that supports 64 thread groups per program type is
configured logically to use only 48 thread groups per program type, the stack
requirement for a 64-item processor still applies. Table 3.5 shows the number of
subentries per stack entry, based on the physical thread-group width of the
processor.
The CALL*, LOOP_START*, and PUSH* instructions each consume a certain
number of stack entries or subentries. These entries are released when the
corresponding POP, LOOP_END, or RETURN instruction is executed. The additional
stack space required by each of these flow-control instructions is described in
Table 3.6.
At any point during the execution of a program, if A is the total number of full
entries in use, and B is the total number of subentries in use, then STACK_SIZE
is calculated by:
A + B / (# of subentries per entry) <= STACK_SIZE
Table 3.5 Stack Subentries
Physical Thread-Group Width of Processor
16 32 48 64
Subentries per Entry 8 8 4 4
Table 3.6 Stack Space Required for Flow-Control Instructions
Instruction
Stack Size per Physical Thread-Group
Width
Comments16 32 48 64
PUSH, PUSH_ELSE when
whole quad mode is not
set, and ALU_PUSH_BEFORE
one
subentry
one
subentry
one
subentry
one
subentry
If a PUSH instruction is invoked, two
subentries on the stack must be
reserved to hold the current active
(valid) masks.
PUSH, PUSH_ELSE when
whole quad mode is set
one entry one entry one entry one entry
LOOP_START* one entry one entry one entry one entry
CALL, CALL_FS two
subentries
one
subentry
one
subentry
one
subentry
A 16-bit-wide processor needs two
subentries because the program
counter has more than 16 bits.
- Reference Guide 1
- Contents 3
- ATI R700 Technology 10
- About This Document 11
- Audience 11
- Organization 11
- Registers 12
- Endian Order 12
- Conventions 12
- Related Documents 13
- Contact Information 13
- Chapter 1 15
- Introduction 15
- Chapter 2 19
- 2.1.1 Data Flows 20
- 2.1.2 Geometry Program Absent 20
- 2.1.3 Geometry Shader Present 21
- 2.2 Instruction Terminology 22
- 2.3 Control Flow and Clauses 24
- 2.5 Program State 26
- Table 2.6 ALU State 28
- Table 2.7 Vertex-Fetch State 29
- Table 2.6 ALU State (Cont.) 29
- 2.6 Data Sharing 30
- Data Sharing 2-13 31
- 2-14 Data Sharing 32
- 2.6.2 Local Data Share (LDS) 33
- 2-16 Data Sharing 34
- Data Sharing 2-17 35
- 2-18 Data Sharing 36
- Chapter 3 37
- Control Flow (CF) Programs 37
- 3.1 CF Microcode Encoding 38
- 3.3.1 ALU Clause Initiation 42
- 3.4.2 Memory Writes 44
- 3.4.3 Memory Reads 45
- 3.6 Conditional Execution 47
- 3-12 Conditional Execution 48
- Conditional Execution 3-13 49
- 3.6.5 Stack Allocation 51
- 3.7.1 ADDR Field 53
- 3.7.3 DirectX9 Loops 54
- 3.7.4 DirectX10 Loops 55
- 3.7.5 Repeat Loops 55
- 3.7.6 Subroutines 56
- Chapter 4 59
- ALU Clauses 59
- 4-2 Overview of ALU Features 60
- 4.6 GPRs and Constants 63
- 4.6.1 Relative Addressing 64
- 4.6.3 Out-of-Bounds Addresses 65
- 4.6.4 ALU Constants 66
- 4.7 Scalar Operands 67
- 4.7.2 Input Modifiers 68
- 4.7.3 Data Flow 68
- Scalar Operands 4-11 69
- 4-12 Scalar Operands 70
- BANK_SWIZZLE src0 src1 src2 70
- 4-16 Scalar Operands 74
- 4.8 ALU Instructions 77
- Floating-Point Operations 79
- 4.9 ALU Outputs 83
- 4.9.2 Destination Registers 84
- 4.9.3 Predicate Output 84
- 4.9.4 NOP Instruction 85
- 4.9.5 MOVA Instructions 85
- Chapter 5 89
- Vertex-Fetch Clauses 89
- 5.2 Constant Sharing 90
- Chapter 6 91
- Texture-Fetch Clauses 91
- 6.2 Constant-Fetch Operations 92
- 6.4 Constant Sharing 92
- Constant Sharing 6-3 93
- 6-4 Constant Sharing 94
- Chapter 7 95
- Memory Read Clauses 95
- 7.2 Cached and Uncached Reads 96
- 7.3 Burst Memory Reads 96
- Chapter 8 97
- Data Share Clauses 97
- Chapter 9 99
- Instruction Set 99
- Initiate ALU Clause 100
- ALU_BREAK 101
- ALU_CONTINUE 102
- ALU_ELSE_AFTER 103
- ALU_POP_AFTER 104
- ALU_POP2_AFTER 105
- ALU_PUSH_BEFORE 106
- Call Subroutine 107
- Call Fetch Subroutine 108
- CUT_VERTEX 109
- EMIT_CUT_VERTEX 111
- Vertex Exported to Memory 112
- EMIT_VERTEX 112
- Export from VS or PS 113
- Export Last Data 114
- EXPORT_DONE 114
- Jump to Address 115
- Kill Pixels Conditional 116
- Break Out Of Innermost Loop 117
- LOOP_BREAK 117
- Continue Loop 118
- LOOP_CONTINUE 118
- End Loop 119
- LOOP_END 119
- Start Loop 120
- LOOP_START 120
- Start Loop (DirectX 10) 121
- LOOP_START_DX10 121
- Enter Loop If Zero, No Push 122
- LOOP_START_NO_AL 122
- Access Scatter Buffer 123
- MEM_EXPORT 123
- Access Reduction Buffer 124
- MEM_REDUCTION 124
- Write Ring Buffer 125
- MEM_RING 125
- Access Scratch Buffer 126
- MEM_SCRATCH 126
- Write Steam Buffer 0 127
- MEM_STREAM0 127
- Write Steam Buffer 1 128
- MEM_STREAM1 128
- Write Steam Buffer 2 129
- MEM_STREAM2 129
- Write Steam Buffer 3 130
- MEM_STREAM3 130
- No Operation 131
- Pop From Stack 132
- Push State To Stack 133
- PUSH_ELSE 134
- Return From Subroutine 135
- Initiate Texture-Fetch Clause 136
- Initiate Vertex-Fetch Clause 137
- WAIT_ACK 139
- 9.2 ALU Instructions 140
- Add Floating-Point, 64-Bit 141
- Add Integer 144
- AND Bitwise 145
- Scalar Arithmetic Shift Right 146
- ASHR_INT 146
- Floating-Point Ceiling 147
- CMOVE_INT 149
- CMOVGE_INT 151
- CMOVGT_INT 153
- Scalar Cosine 154
- Cube Map 155
- Four-Element Dot Product 156
- DOT4_IEEE 157
- Scalar Base-2 Exponent, IEEE 158
- EXP_IEEE 158
- Floating-Point Floor 159
- Floating-Point To Integer 160
- FLT_TO_INT 160
- FLT32_TO_FLT64 161
- FLT64_TO_FLT32 163
- Floating-Point Fractional 165
- FRACT_64 166
- FREXP_64 168
- Integer To Floating-Point 170
- INT_TO_FLT 170
- LDEXP_64 175
- Scalar Base-2 Log 177
- LOG_CLAMPED 177
- Scalar Base-2 IEEE Log 178
- LOG_IEEE 178
- Scalar Logical Shift Left 179
- LSHL_INT 179
- Scalar Logical Shift Right 180
- LSHR_INT 180
- Floating-Point Maximum 181
- MAX_DX10 182
- Integer Maximum 183
- Unsigned Integer Maximum 184
- MAX_UINT 184
- Four-Element Maximum 185
- Floating-Point Minimum 186
- MIN_DX10 187
- Signed Integer Minimum 188
- Unsigned Integer Minimum 189
- MIN_UINT 189
- Copy To GPR 190
- MOVA_FLOOR 192
- MOVA_INT 193
- Floating-Point Multiply 194
- Floating-Point Multiply, IEEE 197
- MUL_IEEE 197
- MUL_LIT_D2 199
- MUL_LIT_M2 200
- MUL_LIT_M4 201
- Floating-Point Multiply-Add 202
- MULADD_64 203
- MULADD_D2 206
- MULADD_M2 207
- MULADD_M4 208
- MULADD_IEEE 209
- MULADD_IEEE_D2 210
- MULADD_IEEE_M2 211
- MULADD_IEEE_M4 212
- MULHI_INT 213
- MULHI_UINT 214
- MULLO_INT 215
- MULLO_UINT 216
- Bit-Wise NOT 218
- Bit-Wise OR 219
- Predicate Counter Clear 220
- PRED_SET_CLR 220
- Predicate Counter Invert 221
- PRED_SET_INV 221
- Predicate Counter Pop 222
- PRED_SET_POP 222
- Predicate Counter Restore 223
- PRED_SET_RESTORE 223
- PRED_SETE 224
- PRED_SETE_64 225
- PRED_SETE_INT 227
- PRED_SETE_PUSH 228
- PRED_SETE_PUSH_INT 229
- PRED_SETGE 230
- PRED_SETGE_64 231
- PRED_SETGE_INT 234
- PRED_SETGE_PUSH 235
- PRED_SETGE_PUSH_INT 236
- PRED_SETGT 237
- PRED_SETGT_64 238
- PRED_SETGT_INT 240
- PRED_SETGT_PUSH 241
- PRED_SETGT_PUSH_INT 242
- PRED_SETLE_INT 243
- PRED_SETLE_PUSH_INT 244
- PRED_SETLT_INT 245
- PRED_SETLT_PUSH_INT 246
- PRED_SETNE 247
- PRED_SETNE_INT 248
- PRED_SETNE_PUSH 249
- PRED_SETNE_PUSH_INT 250
- RECIP_CLAMPED 251
- RECIP_FF 252
- RECIP_IEEE 253
- RECIP_INT 254
- RECIP_UINT 255
- RECIPSQRT_CLAMPED 256
- RECIPSQRT_FF 257
- RECIPSQRT_IEEE 258
- Floating-Point Set If Equal 260
- SETE_DX10 261
- Integer Set If Equal 262
- SETE_INT 262
- SETGE_DX10 264
- SETGE_INT 265
- SETGE_UINT 266
- SETGT_DX10 268
- SETGT_INT 269
- SETGT_UINT 270
- SETNE_DX10 272
- Integer Set If Not Equal 273
- SETNE_INT 273
- Scalar Sine 274
- SQRT_IEEE 275
- Integer Subtract 276
- Floating-Point Truncate 277
- UINT_TO_FLT 278
- Bit-Wise XOR 279
- 9.3 Vertex-Fetch Instructions 280
- Semantic Vertex Fetch 281
- SEMANTIC 281
- GET_COMP_TEX_LOD 282
- GET_GRADIENTS_H 283
- GET_GRADIENTS_V 284
- Get Number of Samples 285
- GET_NUMBER_OF_SAMPLES 285
- Get Texture Resolution 286
- GET_TEXTURE_RESINFO 286
- Keep Gradients 287
- KEEP_GRADIENTS 287
- Load Texture Elements 288
- Memory Read 289
- Sample Texture 290
- SAMPLE_C 291
- SAMPLE_C_G 292
- SAMPLE_C_G_L 293
- SAMPLE_C_G_LB 294
- SAMPLE_C_G_LZ 295
- Sample Texture with LOD 296
- SAMPLE_C_L 296
- Sample Texture with LOD Bias 297
- SAMPLE_C_LB 297
- Sample Texture with LOD Zero 298
- SAMPLE_C_LZ 298
- Sample Texture with Gradient 299
- SAMPLE_G 299
- SAMPLE_G_L 300
- SAMPLE_G_LB 301
- SAMPLE_G_LZ 302
- SAMPLE_L 303
- SAMPLE_LB 304
- SAMPLE_LZ 305
- Set Cubemap Index 306
- SET_CUBEMAP_INDEX 306
- Set Horizontal Gradients 307
- SET_GRADIENTS_H 307
- Set Vertical Gradients 308
- SET_GRADIENTS_V 308
- 9.5 Memory Read Instructions 309
- Read Reduction Buffer 310
- REDUCTION 310
- Read Scatter Buffer 311
- Local Data Share Write 312
- LOCAL_DS_WRITE 312
- Local Data Share Read 313
- LOCAL_DS_READ 313
- LOCAL_DS_READ, opcode 5 (0x5) 313
- Chapter 10 315
- Microcode Formats 315
- Control Flow Doubleword 0 317
- CF_WORD0 317
- Control Flow Doubleword 1 318
- CF_WORD1 318
- Control Flow ALU Doubleword 0 321
- CF_ALU_WORD0 321
- Control Flow ALU Doubleword 1 322
- CF_ALU_WORD1 322
- CF_ALLOC_EXPORT_WORD0 324
- CF_ALLOC_EXPORT_WORD1 326
- CF_ALLOC_EXPORT_WORD1_BUF 328
- 10.2 ALU Instructions 329
- ALU Doubleword 0 330
- ALU_WORD0 330
- ALU Doubleword 0 (Cont.) 331
- ALU_WORD1_OP2_V2 332
- ALU_WORD1_OP3 337
- Vertex Fetch Doubleword 0 340
- Vertex Fetch Doubleword 1 341
- VTX_WORD1 341
- VTX_WORD1_GPR 344
- VTX_WORD1_SEM 346
- Texture Fetch Doubleword 0 349
- TEX_WORD0 349
- Texture Fetch Doubleword 1 351
- TEX_WORD1 351
- 10.5 Memory Read Instructions 352
- MEM_RD_WORD0 353
- MEM_RD_WORD1 355
- MEM_RD_WORD2 357
- MEM_DSW_WORD0 358
- MEM_DSW_WORD1 359
- MEM_DSW_WORD2 360
- MEM_DSR_WORD0 361
- MEM_DSR_WORD1 362
- MEM_DSR_WORD2 363
- Appendix A 365
- Instruction Table 365
- Glossary of Terms 373
- ATI STREAM COMPUTING 374
- Glossary-10 382
- Index-10 392
Related products and manuals for Paper shredders Boxis R700
Paper shredders Boxis S700 User Manual
(14 pages)
(14 pages)
Paper shredders Boxis R510 User Manual
(8 pages)
(8 pages)
Paper shredders Boxis R510 User Manual
(4 pages)
(4 pages)
© 2020, manymanuals.com. All rights reserved. | 2.211 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals