Boxis R700 User Manual download pdf (Page 70)

ATI R700 Technology

4-12 Scalar Operands

Each ALU.Trans operation can reference at most two constants of any type. For

example, all of the following are legal, and the four slots shown can occur as a

single instruction group:

GPR0.X <= C0.X + GPR0.X

GPR0.Y <= 1.0 + C1.Y // Can mix cfile and non-cfile in one

instruction group.

GPR0.Z <= C2.X + GPR0.Z // Multiple reads from cfile X bank are OK.

GPR0.W <= C3.Z + C0.X // Reads from four distinct cfile addresses

are OK.

4.7.6 Literal Constant Restrictions

A literal constant is fetched if any source operand refers to the literal constant,

regardless of whether the operand is used by the instruction group; so, be sure

to clear unused operands in instruction fields. If all operands referencing the

literal refer only to the X and Y vector elements, a two-element literal (one slot)

is fetched. If any operand referencing the literal refers to the Z or W vector

elements, a four-element literal (two slots) is fetched. An ALU.Trans operation

can reference at most two constants of any type.

4.7.7 Cycle Restrictions for ALU.[X,Y,Z,W] Units

For ALU.[X,Y,Z,W] operations, source operands src0, src1, and src2 are loaded

during three cycles. At most one GPR.X, one GPR.Y, one GPR.Z and one

GPR.W can be read per cycle. The GPR values requested on cycle N are

assembled into a four-element vector, CYCLEN_GPR. In addition, four constant

elements are sent to the pipeline from a combination of sources: the constant-

elements sent on cycle N are assembled into a four-element vector, CYCLEN_K.

Collectively, these two vectors are referred to as CYCLEN_DATA.

The values in CYCLEN_DATA populate the logical operands src[0, 2]. The mapping

of CYCLE[0, 2]_DATA to src[0, 2] must be specified in the microcode, using the

BANK_SWIZZLE field. Read port restrictions must be respected across the

instructions in an instruction group, described below. Each slot has its own

BANK_SWIZZLE field, and these fields can be coordinated to avoid the read port

restrictions.

For ALU.[X,Y,Z,W] operations, BANK_SWIZZLE specifies from which cycle each

operand data comes from, if the operand’s source is GPR data. Constant data

for srcN is always from CYCLEN_K. The setting, ALU_VEC_012, is the identity

setting that loads operand N using data in CYCLEN_GPR.

BANK_SWIZZLE src0 src1 src2

ALU_VEC_012 CYCLE0_GPR CYCLE1_GPR CYCLE2_GPR

ALU_VEC_021 CYCLE0_GPR CYCLE2_GPR CYCLE1_GPR

ALU_VEC_120 CYCLE1_GPR CYCLE2_GPR CYCLE0_GPR

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Boxis R700 User Manual Page 70