Boxis R700 User Manual Page 67

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ATI R700 Technology
Scalar Operands 4-9
Copyright © 2009 Advanced Micro Devices, Inc. All rights reserved.
4.6.4.5 Dynamically-Indexed Constant Access (AR-relative, Constant Waterfalling)
To support DX9 vertex shaders, we provide dynamic indexing of constant-file
constants. This means that a GPR value is used as the index into the constant
file. Since the value comes from a GPR, it can be unique for each pixel. In the
worst case, it may take 64 times as long to execute this instruction, since up to
64 constant-file reads can be required.
Dynamic indexing requires two instructions:
MOVA: Move one element of a GPR into the Address Register (AR) to be used
as the index value.
<any ALU instruction>: Use the indices from the MOVA and perform
the indirect lookup.
There is a two-instruction delay slot between loading and using the GPR index
value. Hardware inserts delays if the kernel does not. The GPR indices loaded
by a MOVA instruction only persist for one clause; at the end of the clause they
are invalidated.
4.6.4.6 ALU Constant Buffer Sharing
ES, GS, and VS kernels can, on a per-ALU-clause basis, access their own
constant buffers or those of the other shader type.
ES/VS can use their own or use GS constant buffers, and GS can use its own
or ES/VS ones. This is provided for cases when the GS and VS shaders can be
merged into a single hardware shader stage.
This capability is activated by setting the ALT_CONSTS bit in the
SQ_CF_ALU_WORD1.
4.7 Scalar Operands
For each instruction, the operands src0, src1, and src2 are specified in the
instruction’s SRC*_SEL and SRC*_ELEM fields. GPR and constant-register
addresses can be relative-addressed, as specified in the SRC*_REL and
INDEX_MODE fields. In the OP2 microcode format, src2 is undefined.
4.7.1 Source Addresses
The data source address is specified in the SRC*_SEL field. This can refer to one
of the following.
A GPR address, GPR[0, 127], with values [0, 127].
A kcache constant in bank 0, kcache0[0, 31], with values [128, 159];
kcache0[16, 31] are accessible only if two cache lines have been locked.
A kcache constant in bank 1, kcache1[0, 31], with values [160, 191];
kcache1[16, 31] are accessible only if two cache lines are locked.
A constant-register address, c[0, 255], with values [256, 511].
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