Boxis R700 User Manual download pdf (Page 92)

ATI R700 Technology

6-2 Constant-Fetch Operations

Figure 6.1 Texture-Fetch Microcode-Format 4-Tuple

6.2 Constant-Fetch Operations

The buffer ID space, specified in the RESOURCE_ID field of the TEX_DWORD0

microcode format, is eight bits wide, allowing constant and texture fetch to

coexist in the same ID space. The two types of fetches differ according to the

manner in which their resources are organized.

6.3 FETCH_WHOLE_QUAD and WHOLE_QUAD_MODE

The processor executes pixel threads in groups of four, called quads. Sometimes

the edge of a primitive (such as a triangle) cuts through a quad so that some

pixels in the quad are outside the primitive. The threads executing these pixels

are placed in the invalid state.

The following two features are sometimes helpful when computing the inputs to

gradient operations:

• Texture-fetch instructions contain a bit (FETCH_WHOLE_QUAD) if this bit is set

the fetches from invalid pixels are still executed.

• Within a quad, some pixels may have the active Mask set to execute while

others may be set to skip. Normally the pixels which are set to skip, to do

NOT execute instructions, however if the WHOLE_QUAD_MODE bit is set, the all

four thread in the quad execute if at least one pipeline is set to execute.

6.4 Constant Sharing

ES, GS, and VS kernels can, on a per-clause basis, either their own texture and

sampler constants or those of the other shader type.

ES/VS can use their own or use GS constant buffers, and GS can use its own

or ES/VS ones. This is for cases when the GS and VS shaders can be merged

into a single hardware shader stage.

31 24 23 16 15 8 7 0

00000000000000000000000000000000 +12

TEX_DWORD2 +8

TEX_DWORD1 +4

TEX_DWORD0 +0

<------------ LSB ------------>

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Boxis R700 User Manual Page 92